Target architecture - RISC-V RV32IM
Phase 1: Registers and instructions based on RISC-V RV32IM
Registers
x0
Hardwired zero
x1
ra
Return address
x2
sp
Stack pointer
x3
gp
Global pointer
x4
tp
Thread pointer
x5
t0
Temporary register
x6
t1
Temporary register
x7
t2
Temporary register
x8
s0
Platform register
x9
s1
Platform register
x10
a0
Argument register
x11
a1
Argument register
x12
a2
Temporary register
x13
a3
Temporary register
x14
a4
Temporary register
x15
a5
Temporary register
x16
a6
Temporary register
x17
a7
Temporary register
x18
s2
Saved register
x19
s3
Saved register
x20
s4
Saved register
x21
s5
Saved register
x22
s6
Saved register
x23
s7
Saved register
x24
s8
Saved register
x25
s9
Saved register
x26
s10
Saved register
x27
s11
Saved register
x28
t3
Temporary register
x29
t4
Frame pointer
x30
t5
Return address
x31
t6
Integer register
Instructions:
We support RISC-V32 instruction sets I and M:
LUI
Load Upper Immediate: Loads a 20-bit immediate value into the upper 20 bits of a register, zero-filling the lower 12 bits.
AUIPC
Add Upper Immediate to PC: Adds a 20-bit immediate value to the current program counter (PC), storing the result in a register. This is often used for generating global addresses.
JAL
Jump and Link: Performs an unconditional jump to a target address and saves the address of the next instruction (PC+4) in a register.
JALR
Jump and Link Register: Jumps to a target address specified in a register and saves the address of the next instruction (PC+4) in a register.
BEQ
Branch if Equal: Branches to a target address if two registers are equal.
BNE
Branch if Not Equal: Branches to a target address if two registers are not equal.
BLT
Branch if Less Than: Branches to a target address if one register is less than another.
BGE
Branch if Greater Than or Equal: Branches to a target address if one register is greater than or equal to another.
BLTU
Branch if Less Than Unsigned: Branches to a target address if one register is less than another (unsigned comparison).
BGEU
Branch if Greater Than or Equal Unsigned: Branches to a target address if one register is greater than or equal to another (unsigned comparison).
LB
Load Byte: Loads a signed byte from memory into a register.
LH
Load Halfword: Loads a signed halfword (2 bytes) from memory into a register.
LW
Load Word: Loads a word (4 bytes) from memory into a register.
LBU
Load Byte Unsigned: Loads an unsigned byte from memory into a register.
LHU
Load Halfword Unsigned: Loads an unsigned halfword from memory into a register.
SB
Store Byte: Stores the low 8 bits of a register into memory.
SH
Store Halfword: Stores the low 16 bits of a register into memory.
SW
Store Word: Stores the full 32 bits of a register into memory.
ADDI
Add Immediate: Adds an immediate value to a register and stores the result in a register.
SLTI
Set Less Than Immediate: Sets a register to 1 if it is less than an immediate value; otherwise, sets it to 0.
SLTIU
Set Less Than Immediate Unsigned: Sets a register to 1 if it is less than an immediate value (unsigned comparison); otherwise, sets it to 0.
XORI
XOR Immediate: Performs a bitwise XOR operation between a register and an immediate value, storing the result in a register.
ORI
OR Immediate: Performs a bitwise OR operation between a register and an immediate value, storing the result in a register.
ANDI
AND Immediate: Performs a bitwise AND operation between a register and an immediate value, storing the result in a register.
SLLI
Shift Left Logical Immediate: Shifts the bits in a register left by an immediate amount and stores the result in a register.
SRLI
Shift Right Logical Immediate: Shifts the bits in a register right by an immediate amount, filling with zeros, and stores the result in a register.
SRAI
Shift Right Arithmetic Immediate: Shifts the bits in a register right by an immediate amount, sign-extending the most significant bit, and stores the result in a register.
ADD
Addition: Adds two registers and stores the result in a third register.
SUB
Subtraction: Subtracts one register from another and stores the result in a third register.
SLL
Shift Left Logical: Shifts the bits in one register left by the number of bits specified in another register and stores the result in a third register.
SLT
Set Less Than: Sets a register to 1 if one register is less than another; otherwise, sets it to 0.
SLTU
Set Less Than Unsigned: Sets a register to 1 if one register is less than another (unsigned comparison); otherwise, sets it to 0.
XOR
XOR: Performs a bitwise XOR operation between two registers and stores the result in a third register.
OR
OR: Performs a bitwise OR operation between two registers and stores the result in a third register.
AND
AND: Performs a bitwise AND operation between two registers and stores the result in a third register.
MUL
Multiply
MULH
Multiply High (signed)
MULHSU
Multiply High (signed)
MULHU
Multiply High (unsigned)
DIV
Divide
DIVU
Divide (unsigned)
REM
Remainder
REMU
Remainder (unsigned)
Reference
[1]. https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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